Pranav M
@pranav0x2212Hardware enthusiast · Interested in Computer Architecture, Processing In Memory, and RTL development
Language Breakdown
Lines of code distribution across 49 owned repositories
Generalist Developer
G-shapedVersatile across many languages and paradigms
Collaboration Network
Global Impact visualization
Repos
68
PRs
0
Growth
+18%
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Coding Streak
Contribution activity over the past year
Manasvi M T
@svisvi413
Nithilan Rameshkumar
@nithitsuki
Ezra Wolf
@EzraWolf
Saankhya
@SaankLeo
Navneet
@NavneetNayak
Top Repositories
all embedded codes lol
Aletheia is an experimental framework for exploring processing-near-memory concepts and data-local computation on commodity hardware.
Resona is a RISC-V DSP simulator with support for the RV32I base and 'P' (DSP) extension
RISCape is a 5-stage pipelined RISC-V processor
Aetheron is a minimal RISC-V SoC using a TileLink-lite interconnect and basic peripherals that can run bare metal C programs
Specula is a Out-of-Order RISC-V RV32I core featuring basic Dynamic Scheduling and Register Renaming. Designed for simulation (WIP)
Verilog Template for IHP 26a Tiny Tapeout Submission
A lightweight OFDM modem simulator with constellation visualization.
A personal lab of notes, papers, and code across hardware and systems.
Hardware implementation of CHIP-8 in Verilog
Open Source Impact
Contributions to external projects
